A Phase Locked Loop (PLL) consists of a Voltage Controlled Oscillator (VCO), the output frequency of which is monitored and controlled. An error voltage steers the VCO and brings it back onto the correct frequency. The error voltage is generated by a Phase Sensitive Detector (PSD) which compares the VCO frequency with a reference frequency.
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Many beginners trying out their skill with QRP TX, for the first time have to overcome many problems before they are able to come on the air. On usual complaint is that, every thing is working fine but the signal is not going out. Here is a simple set up which will enable them to [...]
An RF detector with a dynamic range of 40 dB can now be obtained from Linear Technology (http://www.lineartech. com/pdf/5505i.pdf). The type LTC5505, housed in an SOT23 SMD package, can handle input frequencies between 300 MHz and 3 GHz for input signal levels between –32 dBm and +18 dBm (0 dBm = 1 mW into 50 [...]
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